10-10 august 1997 ad7545 12-bit, buffered, multiplying cmos dac features ? 12-bit resolution ? low gain t.c. 2ppm/ o c (typ) ? fast ttl/cmos compatible data latches ? single +5v to +15v supply ? low power ? low cost ? /883 processed versions available description the ad7545 is a low cost monolithic 12-bit, cmos multiplying dac with on-board data latches. data is loaded in a single 12-bit wide word which allows interfacing directly to most 12-bit and 16-bit bus systems. loading of the input latches is under the control of the cs and wr inputs. a logic low on these control inputs makes the input latches transpar- ent allowing direct unbuffered operation of the dac. ordering information part number temp. range ( o c) package pkg. no. ad7545jn 0 to 70 20 ld pdip e20.3 AD7545KN 0 to 70 20 ld pdip e20.3 ad7545an -40 to 85 20 ld pdip e20.3 ad7545bn -40 to 85 20 ld pdip e20.3 pinout ad7545 (pdip) top view functional diagram 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 out 1 agnd dgnd db11 (msb) db10 db9 db7 db8 db6 db5 r fb v dd wr cs v ref db0 (lsb) db1 db2 db3 db4 12-bit multiplying dac db11 - db0 (pins 4 - 15) 12 12 input data latches 19 17 16 2 1 3 18 20 r fb r out1 agnd v dd dgnd v ref wr cs ad7545 file number 3108.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999
10-11 absolute maximum ratings thermal information supply voltage (v dd to dgnd) . . . . . . . . . . . . . . . . . . . -0.3v, +17v digital input voltage to dgnd . . . . . . . . . . . . . . . .-0.3v, v dd +0.3v v rfb , v ref to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25v v pin1 to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3v, v dd +0.3v agnd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3v, v dd +0.3v operating conditions temperature ranges commercial (j, k, grades) . . . . . . . . . . . . . . . . . . . . .0 o c to 70 o c industrial (a, b, grades) . . . . . . . . . . . . . . . . . . . . . -40 o c to 85 o c extended (s grades) . . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c thermal resistance (typical, note 1) q ja ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 maximum junction temperature (pdip package) . . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . .-65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . 300 o c caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. note: 1. q ja is measured with the component mounted on an evaluation pc board in free air. electrical speci?cations t a = see note 2, v ref = +10v, v out1 = 0v, agnd = dgnd, unless otherwise speci?ed parameter test conditions v dd = +5v v dd = +15v units min typ max min typ max static performance resolution 12 12 bits relative accuracy j, a, s - - 2- - 2 lsb k, b - - 1- - 1 lsb differential nonlinearity j, a, s 10-bit monotonic t min to t max -- 4- - 4 lsb k, b 12-bit monotonic t min to t max -- 1- - 1 lsb gain error (using internal rfb) j, a, s dac register loaded with 1111 1111 1111 -- 20 - - 25 lsb k, b gain error is adjustable using the circuits of figures 4 and 5 (note 3) -- 10 - - 15 lsb gain temperature coefficient d gain/ d temperature typical value is 2ppm/ o c for v dd = +5v (note 4) -- 5- - 10 ppm/ o c dc supply rejection d gain/ d v dd d v dd = 5% 0.015 - 0.03 0.01 - 0.02 % output leakage current at out1 j, k db0 - db11 = 0v; wr, cs = 0v (note 2) - - 50 - - 50 na a, b - -50- -50na s - - 200 - - 200 na dynamic characteristics current setting time to 1 / 2 lsb, out1 load = 100 w , dac output measured from falling edge of wr, cs = 0v (note 4) - -2- -2 m s propagation delay from digital input change to 90% of final analog output out1 load = 100 w, c ext = 13pf (notes 4 and 5) - - 300 - - 250 ns digital to analog glitch impulse v ref = agnd - 400 - - 250 - nv/s ac feedthrough at out1 v ref = 10v, 10khz sinewave (note 6) -5- -5-mv p-p analog outputs output capacitance c out1 db0 - db11 = 0v, wr, cs = 0v (note 4) - - 70 - - 70 pf c out1 db0 - db11 = v dd , wr, cs = 0v (note 4) - - 200 - - 200 pf ad7545
10-12 reference input input resistance (pin 19 to gnd) input resistance tc = -300ppm/ o c (typ) 7- -7- -k w typical input resistance = 11k w - - 25 - - 25 k w digital inputs input high voltage, v ih 2.4 - - - - 13.5 v input low voltage, v il - - 0.8 - - 1.5 v input current, i in v in = 0 or v dd (note 7) 1- 10 1- 10 m a (max) input capacitance db0 - db11 v in = 0 (note 4) - - 7 - - 7 pf wr, cs v in = 0 (note 4) - - 20 - - 20 pf switching characteristics (note 4) chip select to write setup time, t cs see figure 1 380 200 - 200 120 - ns chip select to write hold time, t ch see figure 1 0 - - 0 - - ns write pulse width, t wr t cs 3 t wr , t ch 3 0, see figure 1 400 175 - 240 100 ns data setup time, t ds see figure 1 210 100 - 120 60 - ns data hold time, t dh see figure 1 10 - - 10 - - ns power supply characteristics i dd all digital inputs v il or v ih - -2- -2ma all digital inputs 0v or v dd - 100 500 - 100 500 m a all digital inputs 0v or v dd -10- -10- m a notes: 2. temperature ranges as follows: j, k versions: 0 o c to 70 o c a, b versions: -20 o c to 85 o c s version: -55 o c to 125 o c t a = 25 o c for typ speci?cations. min and max are measured over the speci?ed operating range. 3. this includes the effect of 5ppm maximum gain tc. 4. parameter not tested. parameter guaranteed by design, simulation, or characterization. 5. db0 - db11 = 0v to v dd or v dd to 0v in plastic and sidebraze package. 6. feedthrough can be further reduced by connecting the metal lid on the ceramic package to dgnd. 7. logic inputs are mos gates. typical input current (25 o c) is less than 1na. 8. typical values are not guaranteed but reflect mean performance specification. specifications subject to change without notice. electrical speci?cations t a = see note 2, v ref = +10v, v out1 = 0v, agnd = dgnd, unless otherwise speci?ed (continued) parameter test conditions v dd = +5v v dd = +15v units min typ max min typ max timing diagrams figure 1a. typical write cycle figure 1b. preferred write cycle figure 1. write cycle timing diagram data valid chip select write data in (db0 - db11) v dd 0 v dd v dd 0 0 t cs t wr t ds t dh t ch data valid chip select write data in (db0 - db11) v dd 0 v dd v dd 0 0 t cs t wr t ds t dh t ch ad7545
10-13 circuit information - d/a converter section figure 2 shows a simpli?ed circuit of the d/a converter section of the ad7545. note that the ladder termination resistor is connected to agnd. r is typically 11k w . the binary weighted currents are switched between the out1 bus line and agnd by n-channel switches, thus maintaining a constant current in each ladder leg independent of the switch state. one of the current switches is shown in figure 3. the capacitance at the out1 bus line, c out1 , is code dependent and varies from 70pf (all switches to agnd) to 200pf (all switches to out1). the input resistance at v ref (figure 2) is always equal to r ldr (r ldr is the r/2r ladder characteristic resistance and is equal to the value r). since r in at the v ref pin is constant, the reference terminal can be driven by a reference voltage or a reference current, ac or dc, of positive or negative polarity. (if a current source is used, a low temperature coef?cient external r fb is recommended to de?ne scale factor). circuit information - digital section figure 4 shows the digital structure for one bit. the digital signals control and contr ol are generated from cs and wr. the input buffers are simple cmos inverters designed such that when the ad7545 is operated with v dd = 5v, the buffers convert ttl input levels (2.4v and 0.8v) into cmos logic levels. when v in is in the region of 2.0v to 3.5v the input buffers operate in their linear region and draw current from the power supply. to minimize power supply currents it is recommended that the digital input voltages be as close to the supply rails (v dd and dgnd) as is practically possible. the ad7545 may be operated with any supply voltage in the range 5v v dd 15v. with v dd = +15v the input logic levels are cmos compatible only, i.e., 1.5v and 13.5v. application output offset cmos current-steering d/a converters exhibit a code dependent output resistance which in turn causes a code dependent ampli?er noise gain. the effect is a code depen- dent differential nonlinearity term at the ampli?er output which depends on v os where v os is the ampli?er input offset voltage. to maintain monotonic operation it is recom- mended that v os be no greater than (25 x 10 -6 ) (v ref ) over the temperature range of operation. general ground management ac or transient voltages between agnd and dgnd can cause noise injection into the analog output. the simplest method of ensuring that voltages at agnd and dgnd are equal is to tie agnd and dgnd together at the ad7545. in more complex systems where the agnd and dgnd con- nection is on the backplane, it is recommended that two diodes be connected in inverse parallel between the ad7545 agnd and dgnd pins (1n914 or equivalent). digital glitches when wr and cs are both low the latched are transparent and the d/a converter inputs follow the data inputs. in some mode selection write mode: cs and wr low, dac responds to data bus (db0 - db11) inputs hold mode: either cs or wr high, data bus (db0 - db11) is locked out; dac holds last data present when wr or cs assumed high state. notes: 9. v dd = +5v; t r = t f = 20ns 10. v dd = +15v; t r = t f = 40ns 11. all input signal rise and fall times measured from 10% to 90% of v dd . 12. timing measurement reference level is (v ih + v il )/2. 13. since input data latches are transparent for cs and wr both low, it is preferred to have data valid before cs and wr both go low. this prevents undesirable changes at the analog output while the data inputs settle. db11 (msb) v ref rrr r 2r 2r 2r 2r 2r 2r r fb out1 agnd db10 db9 db1 db0 (lsb) figure 2. simplified d/a circuit of ad7545 to ladder from interface logic agnd out1 figure 3. n-channel current steering switch figure 4. digital input structure control contr ol inputs buffers to out1 switch to agnd switch ad7545
10-14 bus systems, data on the data bus is not always valid for the whole period during which wr is low and as a result invalid data can brie?y occur at the d/a converter inputs during a write cycle. such invalid data can cause unwanted glitches at the output of the d/a converter. the solution to this prob- lem, if it occurs, is to retime the write pulse ( wr) so that it only occurs when data is valid. another cause of digital glitches is capacitive coupling from the digital lines to the out1 and agnd terminals. this should be minimized by isolating the analog pins of the ad7545 (pins 1, 2, 19, 20) from the digital pins by a ground track run between pins 2 and 3 and between pins 18 and 19 of the ad7545. note how the analog pins are at one end of the package and separated from the digital pins by v dd and dgnd to aid isolation at the board level. on-chip capacitive coupling can also give rise to crosstalk from the digital to analog sections of the ad7545, particularly in circuits with high currents and fast rise and fall times. this type of crosstalk is minimized by using v dd = +5v. however, great care should be taken to ensure that the +5v used to power the ad7545 is free from digitally induces noise. temperature coef?cients the gain temperature coef?cient of the ad7545 has a maxi- mum value of 5ppm/ o c and a typical value of 2ppm/ o c. this corresponds to worst case gain shifts of 2 lsbs and 0.8 lsbs respectively over a 100 o c temperature range. when trim resistors r1 and r2 are used to adjust full scale range, the temperature coef?cient of r1 and r2 should also be taken into account. basic applications figures 5 and 6 show simple unipolar and bipolar circuits using the ad7545. resistor r1 is used to trim for full scale. capacitor c1 provides phase compensation and helps pre- vent overshoot and ringing when using high speed op amps. note that the circuits of figures 5 and 6 have constant input impedance at the v ref terminal. the circuit of figure 4 can either be used as a ?xed reference d/a converter so that it provides an analog output voltage in the range 0v to -v in (note the inversion introduced by the op amp) or v in can be an ac signal in which case the circuit behaves as an attenuator (2-quadrant multiplier). v in can be any voltage in the range -20v v in +20v (provided the op amp can handle such voltages) since v ref is permitted to exceed v dd . table 2 shows the code relationship for the circuit of figure 4. figure 5 and table 3 illustrate the recommended circuit and code relationship for bipolar operation. the d/a function itself uses offset binary code and inverter u 1 on the msb line con- verts 2s complement input code to offset binary code. if appro- priate, inversion of the msb may be done in software using an exclusive -or instruction and the inverter omitted. r3, r4 and r5 must be selected to match within 0.01% and they should be the same type of resistor (preferably wire-wound or metal foil), so that their temperature coef?cients match. mismatch of r3 value to r4 causes both offset and full scale error. mismatch of r5 to r4 and r3 causes full scale error. the choice of the operational ampli?ers in figure 4 and figure 5 depends on the application and the trade off between required precision and speed. below is a list of operational ampli?ers which are good candidates for many applications. the main selection criteria for these operational ampli?ers is to have low v os , low v os drift, low bias current and low settling time. these ampli?ers need to maintain the low nonlinearity and monotonic operation of the d/a while providing enough speed for maximum converter performance. operational ampli?ers ha5127 ultra low noise, precision ha5137 ultra low noise, precision, wide band ha5147 ultra low noise, precision, high slew rate ha5170 precision, jfet input table 1. recommended trim resistor values vs grades for v dd = +5v trim resistor j, a, s k, b r1 500 w 200 w r2 150 w 68 w table 2. unipolar binary code table for circuit of figure 4 binary number in dac register analog output 1111 1111 1111 1000 0000 0000 0000 0000 0001 0000 0000 0000 0v table 3. 2s complement code table for circuit of figure 5 data input analog output 0111 1111 1111 0000 0000 0001 0000 0000 0000 0v 1111 1111 1111 1000 0000 0000 v in 4095 4096 ------------ - ?t y C v in 2048 4096 ------------ - ?t y C 1 2 -- - v in C = v in 1 4096 ------------ - ?t y C +v in 2047 2048 ------------ - ?t y +v in 1 2048 ------------ - ?t y v in 1 2048 ------------ - ?t y C v in 2048 2048 ------------ - ?t y C ad7545
10-15 figure 5. unipolar binary operation figure 6. bipolar operation (2s complement code) + - 3 18 20 19 17 16 ad7545 out 1 agnd dgnd v ref v dd r fb 1 2 r1 * v in wr cs db11 - db0 (pins 4 - 15) analog common r2 (note) v dd v out c1 33pf note: refer to table 1 a1 3 18 20 19 17 16 ad7545 out 1 agnd dgnd v ref v dd r fb 1 2 r1 (note) v in wr cs db10 - db0 data input analog common r2 (note) v dd r4 c1 33pf + - v out a2 20k r5 20k r3 10k r6 5k 4 11 12 u 1 (see text) note: for values of r1 and r2 see table 1 db11 ad7545
10-16 die characteristics die dimensions: 121 mils x 123 mils (3073micrms x 3124micrms) metallization: type: pure aluminum thickness: 10 1k ? passivation: type: psg/nitride psg: 7 1.4k ? nitride: 8 1.2k ? process: cmos metal gate metallization mask layout ad7545 pin 3 dgnd pin 2 agnd pin 1 out1 pin 20 r feedback pin 19 v ref pin 17 wr pin 16 pin 15 pin 14 pin 4 db11 (msb) pin 5 db10 pin 6 db9 pin 7 db8 pin 12 db3 pin 10 db5 pin 9 db6 pin 8 db7 pin 18 v dd cs db0 (lsb) db1 pin 13 db2 pin 11 db4 ad7545 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r speci?cations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of p atents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site http://www.intersil.com
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